Integrated circuit design

Chip design (or chip development ) designated in microelectronics the process of developing a microchip from the first idea to the specification and implementation in a schematic and a layout to the finished circuit.

Design methods

The problems due to the increasing complexity and the cost and time pressures have led to the development of methodologies of chip design. What all methods have in common that masks are used for the photolithography with which a production in semiconductor technology is possible. The differences between the methods consist in the development effort and the design flexibility.

The description of the methodology often depends closely with the desired product together and should be categorized as follows:

• Design as a standard circuit Hardwired full design. This is the classic methodology that provides all the capabilities of semiconductor technology, including analog circuits. This is intended primarily mass products are produced, such as microprocessors, RAM modules and products with special requirements eg analog -to-digital converter, building blocks of automotive electronics.
• Mask programming. The function is defined as a design methodology as above, but the content of integrated memory, by changing the photomask set only the last production step ( wired ) be. Examples: ROM microcontroller.
• Application-specific programming. Based on a standard component existing logic elements therein may be connected by subsequent programming without lithographic masks are needed that again. Examples: PROM, PLD, PLA, FPGA.

• Application-specific design. Used for highly specialized modules in mostly small quantities. Full-custom design
• Semi-custom design Design with standard cells
• Gate array / Sea- of- Gates
• FPGA design. Similar to above, but function is baked firmly in programming, eg with antifuse technology

Full-custom design

The development of the chip, or integrated circuit does not occur with prefabricated cells or circuit parts, but customized to the requirements of the circuit to be designed. Basically, there are analog and digital circuits. In the field of analog circuit technology is used almost exclusively to the full-custom design. One has the possibility to interconnect each such transistor and dimension as it is necessary for the function of the circuit. In the field of digital circuit design of the semi-custom design is often used. However, this restricts the design most strongly, since it is essentially static logic is used. If you want contrast, other logic techniques such as using dynamic logic, one falls back on the more flexible full-custom design.

The full-custom design is much more time consuming because it is not as highly automated as the semi-custom design. However, it offers the possibility to optimize the circuit with respect to power consumption, speed, and the required chip area. Due to the great freedoms in the design and in the execution of the layout enormous potential for optimization.

For the full-custom design the developers will put so-called design kits available from semiconductor manufacturer. These are software libraries for each used design tool, which offer a number of primitive components (transistors, resistors, etc. ) obtained with the corresponding, made out of measurement data circuits, software models for circuit simulation to the developer.

The layout of a full-custom design is generated manually. In this case, the developer may determine and optimize the geometries of the individual transistors and the metal lines. In this case, restrictions on the production in the form of geometrical and electrical rules ( Design Rules) must be complied with.

Semi-custom design

In semi-custom design the freedoms of the developer are further restricted. This, however, the development process becomes easier as is increasing the use of prefabricated elements.

Have lost something in the importance of the gate - array or sea- of- gates. Both are half-finished blocks, where the transistors are placed already. The logical elements are produced by fixing the wiring layers ( metal layers ) with only those photomasks competent. This cost can be saved in principle. The design process is restricted by limited space for wiring. Only certain areas ( wiring channels) are approved for compounds in contrast to Sea- of- Gates In particular, in the gate array. Furthermore, the strengths of the gates are not variable enough. The resulting disadvantages are: High power consumption and low functional density and resulting high unit costs.

Widespread is the design with standard cells. Standard cells are pre-designed elements from simple gates over flip -flops to RAM or processors. Analog blocks, such as analog-to- digital converter are also possible. The cells may be placed anywhere in the layout, but have known electrical and geometrical parameters. These parameters are stored in so-called libraries and retrieved by the development tools. In the circuit layout is generated by graphical lining up and connecting the standard cells. Thus, the development process against the full-custom design is much simpler, because a large part of the circuit simulation can be made ​​at the logical level. At high volumes ( > 100,000 ) of the semi-custom design is the best compromise between the efficiency of the chip design and cost / quality of the resulting block.

In smaller numbers and complex functions, FPGAs offer. The design methodology has approached more and more of the semi-custom design with increasing complexity. In contrast, the logic elements in the FPGA are already present on the chip, and are used by temporary or permanent programming ( burning) connected. Be used pre-produced integrated circuits that have been designed as a standard circuit. A significant savings in time and costs resulting from the fact that the designed function " in the field", ie can be applied in a few minutes with the user on the block. However, a disadvantage is the sometimes very high cost, large sized and power consumption of these components.

Design process ( " Design Flow" )

All complex digital integrated circuits are developed roughly according to the following scheme, which strongly supported on tools for design automation:

Core of the modern design process is a description of the function at a higher level of abstraction that is called RTL ( Register Transfer Level ). Complex functions can here in a hardware description language (similar to a programming language) (addition, multiplication, for example ) entered and the overall function of the input RTL description can be simulated on the computer. As hardware description languages ​​usually VHDL or Verilog are used. A graphic input of the circuit diagram in the RTL or the gate level is possible but for larger circuits usually not practical.

The RTL description is then reacted with a synthesis tool, which operates similar to a compiler, into a gate description, the so-called net-list. This netlist can be simulated again to check the results, since they usually used the same VHDL or Verilog syntax.

The synthesis at behavioral level and the validation specification level are at present (2006 ) is generally not automated in contrast.

In preparation for the production steps are still needed:

• Layout synthesis (starting with partitioning and floorplanning, creating a detailed geometrical arrangement of the cells and connections, the so-called mask layout )
• Static timing analysis (STA)
• Layout verification - check the electrical design rules (ERC ), the geometric and other design rules (DRC ) and netlist comparison ( LVS)
• Tape - Out ( charge on production)

In FPGAs, the layout does not (as in semi - or full-custom designs) for the production of photomasks, but to generate the programming of the compounds used. The steps for Design Rule Check (DRC ) and tape-out account for it.

The clock frequency is limited by the sum of the signal delays through the switching elements and the wiring. Are modern VLSI manufacturing processes with feature sizes of 130 nm ( deep submicron ) or used less, the influence of connections increases the signal propagation delays. This has a reducing effect on the achievable clock frequency with which the device can operate correctly. The results of the layout that is coupled back to the function, which is indeed predictable, but still necessitates further design cycles at target misconduct.

The terms of the gate and the wiring will be added and displayed based on " static timing analysis ". In this case, the critical path is identified. This represents the longest possible path is, the can take a signal during one clock period in the circuit and thus sets the maximum operating frequency of the entire circuit. In this case, manufacturing tolerances and temperature effects are considered. Today's designs scale the clock rates in the system with increasing distance from the core down and / or split the semiconductor into single logical computing units, which then only in a relatively small area but conduct their operations with high frequency and synchronous.

The finished geometry data is transferred to the production, where they are used for the production of photographic masks. The process is known as tape-out, as earlier for magnetic tapes ( tapes ) have been used. Compliance with all design rules is important so that the yield ( yield ) of serviceable components in the factory is as high as possible.