Field Programmable Gate Array

A Field Programmable Gate Array (FPGA ) is an integrated circuit (IC ) of the digital technology, in which a logic circuit can be programmed. The English name can be translated as: in the (application) field -programmable ( logic ) gate array.

Unlike the programming of computers or controllers of the term program here refers only secondarily on the specification of temporal processes in the block, but mainly on the definition of its functional structure. By programming structure rules, the basic functioning of individual universal blocks in the FPGA and their interconnection is first with each set. One therefore speaks of the configuration of an FPGA.

• 6.1 microprocessors
• 6.2 ASICs 6.2.1 Advantages of FPGAs
• 6.2.2 Disadvantages of FPGAs

Principle of operation

The specific configuration of internal structures of various circuits can be implemented in an FPGA. These range from low complexity circuits, such as a simple synchronous counter, to highly complex circuits such as microprocessors. FPGAs are used in all areas of digital technology, but especially where it comes to fast signal processing and flexible modification of the circuit in order to make, for example, subsequent improvements to the implemented functions, without having to directly change the physical hardware.

With the introduction of FPGAs compact, application specific circuits were made possible in small numbers. Today they allow inexpensive and flexible production of complex systems such as cellular base stations as an alternative to the more expensive contract manufacturing by semiconductor manufacturers.

In addition to the FPGAs FPAAs exist (Field Programmable Analogue Array) that do not contain digital, analog, but functional blocks, which can be programmed by the user and connected.

Design and Structure

The essential defining the basic structure of an FPGA is a field ( engl. array) of basic blocks, each with a simple programmable lookup table ( LUT) and a 1- bit register ( flip-flop ). The LUTs can, depending on the number of available inputs, implement any n-variable logic function. The programming of the desired operation is carried out by depositing the defining truth table in the SRAM cells of the LUT, the function calculation by reading them from the memory address determined by the inputs. For a long time LUT structures with 4 binary inputs common. Newer FPGAs go to reduce the expenses for the LUT to LUT compounds for the realization of functions having more inputs on to LUTs with up to 6 inputs.

In addition to the LUTs on the FPGA the interconnection of components in large degrees of freedom configurable. Multiplexer structures in the basic blocks often make very fast local signal paths for integration or bypass the flip-flop, the feedback from the output, for connecting neighboring blocks and the like. For the distant connections between the basic blocks is a huge grid of bus structures, can be connected to the inputs and outputs. Further programmable switch components in the crossing points of the grid permit the signal distribution over the entire chip.

Other components

Further, most common elements of an FPGA are:

• Eingangs-/Ausgangs-Blöcke (English IO block or IOB ) are used for communication with the outside world. Across the terminals of the FPGA are connected to the switching matrix. These blocks can be adapted to the respective application, such as the output voltage to be adapted to the respective standard (TTL / CMOS, etc.).
• One or more clock generators generate from provided at the inputs of all the clocks needed for the application of internal clocks. These may be compared with the input clocks shifted in phase and have a group derived from the respective input clock frequency. Pull amplifier as well as a corresponding interconnection ensure that each clocking used throughout the chip is synchronously available. Modern FPGAs typically have one or more phase - locked loops (PLL ), which can be generated broken clock divisions / multiplications rational. The same purpose is to fulfill delay locked loops ( DLLs) and digital frequency synthesizer (DFS ), which some prefer FPGA manufacturer to the PLL.
• In complex FPGAs additional hardwired functions are included, such as memory blocks (called Block RAM ), which can be used in many ways.
• For tasks of digital signal processing as digital filters and multipliers are included in many FPGAs. These allow particularly fast to multiply two binary numbers without the need for logic cells.
• FPGAs, which are (SoC ) in the area of System-on -a- chip application, usually have a number of complex hardware cores to accommodate a complete system. Hard cores are fixed and immutable circuits of most complex functional blocks, such as microcontrollers or Ethernet interface. Complex hardware cores occupy much less chip area than the same function, implemented with logic blocks would need and are typically three to four times faster than the freely configurable logic of the FPGA. For this circuit parts are not as flexible and can no longer serve their function also be changed.

Manufacturers such as Xilinx now offer SRAM -based FPGAs on, have already been accommodated in the chip package flash memory for configuration and do not need an external flash memory more. They are called integrated circuits having a plurality of chips in one package and multi-die. The charging and starting times of the FPGA stay compared to external memory about the same, however, are optimized by the manufacturer. Another advantage is the protection against illegal copies by reading out the external memory located. Currently and for the foreseeable future, it is not technologically possible to replace the SRAM - based switch cells in an FPGA directly, as in the much smaller CPLDs by flash or EEPROM cells.

Configuration

The programming of LUTs and interconnect structures is typically done once before each use, making the FPGA is configured to a specific function. However, this loses the FPGA again by switching off the supply voltage. In use, the FPGA is therefore usually a kind of EPROM to the side of this dissertation, the configuration, the content itself but is also updatable. The support for regional reprogramming of individual FPGA areas during operation increases.

The term programming in this context is to be understood in contrast to the creation of software for a processor: In a FPGA circuit structures are created using hardware description languages ​​or in the form of schematics and subsequently transferred these data for configuration in the block. In the FPGA by certain switch settings are enabled or disabled, which then results in a concrete implemented digital circuit.

Since the function of the FPGA is only determined by the configuration, the same building block for many applications and various circuits can be used. It can therefore be produced in large numbers, making it in prototypes and small series very inexpensive compared to an application specific integrated circuit ( ASIC). FPGAs are generally slower than for ASICs and not any depth or complicated programmable. The depth of the programmable logic is dependent on the preparation by the manufacturer. Measured by. At the number of logical components, the I / O ports and flip-flops which are located in an FPGA

Differences to CPLDs

Often FPGAs with the digital and also reconfigurable CPLD blocks ( Complex Programmable Logic Devices) be equated or compared. The main differences between FPGAs and CPLDs are:

• CPLDs have, compared to FPGAs on a much simpler structure. You do not have a fine mesh array (field) of logic blocks and flip-flops, but only a configurable switch matrix which can connect various input signals to various output signals. The signals can be combined by logical operations such as AND / OR. This CPLDs have a design from the respective independent, constant signal propagation time. By appropriate design methods, a defined maximum processing time can be achieved ( engl. timing constraints) even in FPGAs.
• CPLDs have comparatively few flip-flops. Especially long shift registers, counters, state storage, and similar circuits that require many flip-flops are to realize only inefficient in CPLDs.
• Have CPLDs, since each IO pin has a flip-flop, mostly very many IO pins that are used in many applications only partially. In applications where only relatively simple digital circuits, so-called glue logic, with a high demand for IO pins is used, CPLDs are usually the better choice.
• CPLDs can work technologically by their simple structure with flash cells in the switching matrices. This is a CPLD immediately after switching (English Power -Up ) operational while reconfigurable FPGA with SRAM cells based only have to go through a charge cycle for the configuration. Some manufacturers are, however, long been FPGAs in flash technology. Since the late 1990s, is observed in the CPLDs an approach to the FPGA SRAM technology. Today, most CPLDs work internally SRAM -based. In some CPLD families is now the basic logical element of the FPGA LUT4 typical flip-flop grouping ( Altera MAX II series).
• CPLDs point with the simpler structure and smaller size and a considerably lower power consumption.

Design steps and tools

Creates the configuration of an FPGA is usually by means of a hardware description language, which are primarily VHDL or Verilog, which describes the overall function of the circuit in the form of structures and procedures. A so-called synthesis tool then creates from these data for a desired block a specific netlist using the available resources in this module. Previously, the hardware description is in the context of the development process simulated by means of simulation tools in their behavior and optimized. A well-known tool is for ModelSim.

The configuration data can also be entered graphically from the Browser or simplicity, in most simple circuits by means of a circuit diagram. The required sequence controllers in the FPGA in turn can be represented by finite automata. The hardware descriptive code is then automatically generated in an intermediate step. In addition, can be created using graphical programming systems such as LabVIEW or Matlab / Simulink or the free Logiflash also circuit modules for an FPGA automatically.

In recent years, several projects were trying to describe hardware implementations for ASICs, FPGAs and CPLDs with the C programming language ( HardwareC, HandelC, BachC ). Current approaches rely directly on the widely used standard languages ​​ANSI C or C . For SystemC synthesis tools do not exist, the practical benefits for specific FPGA developments lies with the abstract behavioral modeling and system simulation significantly accelerated, which is why it has become there to the widespread industry standard. Other approaches use high-level synthesis tools to generate from high-level languages ​​(C / C , MATLAB, Java, UML) design on a register transfer level (VHDL, Verilog ). Examples are Catapult C Synthesis from Mentor Graphics, Accelerated Technologies Impulse CoDeveloper or Cynthesizer from Forte Design Systems.

Manufacturer-specific languages ​​such as Altera HDL ( AHDL ), or even the hardware description language ABEL barely used were also used as UDL / I ( Japan).

For the implementation of embedded systems in FPGAs, there are now tools that offer a design to functional block level, such as Xilinx EDK ( Embedded Development Kit). Function blocks such as FIFOs, processors, serial ports, Ethernet MAC layer, RAM controller, parallel IO, etc. are provided by the manufacturer. These functional units called, IP core, are sometimes referred to as source code, or commonly as an encrypted netlist before and are usually parameterized (eg baud rate for serial asynchronous interfaces or fifo depth or width of the parallel interface ). These are connected by buses with other functional units.

According to the description within the design flow followed by further steps, such as functional simulation, synthesis, implementation ( place and route ) and term- based simulation. Only after the implemented circuit on a real FPGA should be tested.

The programming of the logic blocks can be solved in different ways depending on the FPGA. One can distinguish between methods that make it possible to program the FPGA several times, and methods that allow only a one-time programming. Wherein the repeatedly programmable FPGA configuration in memory cells (for example, SRAM, EPROM, EEPROM, Flash) is saved. At the one-time programmable FPGAs, the physical properties of the communication paths permanently changed ( antifuse technology) are. This technology offers the field a greater security against external disturbances.

For FPGA circuit design a synchronous circuit design is recommended, although not mandatory. This means to all flip-flops in a so-called clock domain based on the same clock. Is controlled by the data acquisition in a flip-flop only about the present in addition Clock Enable inputs and not divided clock signals ( engl. gated clocks ). This avoids difficult to handle run-time effects. Some FPGAs offer special clock switches that allow guaranteed trouble-free switching ( glitch -free) between different clock sources during operation.

Areas of application

FPGAs have in recent years its scope from the classic " glue logic ", ie the pure compound logic between various digital components, increasingly expanded and now also used in medium quantities for the realization of complex digital circuits to complete digital systems. Through the reconfigurability of FPGAs directly by the end user is beyond the significant advantage of being able to react to the latest technical developments and the digital circuits to adapt through updates without having to directly modify the underlying hardware of the FPGA chips.

FPGAs are used for example for real-time processing of simple to complex algorithms for digital signal processing in the context of digital filters or fast Fourier transform. But protocol implementations as part of the Ethernet MAC layer, the coding of digital video signals, encryption of data and error correction methods are application areas.

Especially in areas where algorithms or protocols rapid development subject to the use of reconfigurable FPGAs instead of ASICs is attached. The advantages are speed to market, subsequent fixes, adaptation to new developments.

For some classes of computational problems and FPGA - based parallel computers are very suitable. Probably the best known example are FPGA computer to break cryptographic techniques, such as the Data Encryption Standard ( DES). Composed of 120 FPGAs parallel computer COPACOBANA is such a parallel computer for code breaking.

The now reached the number of logic blocks allows the integration of multiple embedded computer systems in a single FPGA chip, including CPU (s), bus system ( s), RAM, ROM, RAM controller, peripheral controller, etc. Such complete systems as a system on a Chip (SoC) respectively. Due to their reconfigurability SRAM and Flash-based FPGAs are the basis for reconfigurable computer.

Digital storage is often implemented with FPGAs, since their numbers are usually too small to design an ASIC for this application. Using fast digital storage per channel, several A / D converters in parallel, which sampling phase the signal to be measured. This requires a very high degree of parallel data processing and storage, for FPGAs are well suited. Oscilloscopes FPGA-based, for example, trigger on very short pulses below the sampling rate of the A / D converters or its emergence count. One benefit of using FPGAs is generally also the fact that different than DSPs relatively low development costs in new designs arise if one of the ICs used is no longer available and its function can be integrated into an existing block.

FPGAs are very often used as a development platform for the digital part of ASICs in order to verify the function. This is necessary because, due to the complexity of today's circuits sole simulations would be too time-consuming.

A particularly tailored to FPGA daughter card standard is the FPGA Mezzanine Card.

History

FPGAs developed in the mid- 1980s as part of its own range of semiconductor devices. As a precursor of FPGAs can remove the circuitry combination of Programmable Read - Only Memory (PROM ) and programmable logic circuits (english programmable logic device PLD) are considered. The combination of reprogrammable memory elements for the realization of logical links in the form of an " array " on a semiconductor chip was patented in 1985 by David Page and Westminster Luverne R. Peterson, but not implemented commercially.

The first commercially available FPGA XC2064 which was the block of Ross Freeman and Bernard Vonderschmitt, both founders of the company Xilinx, was developed in 1985. The XC2064 consisted of configurable logic blocks 64, called the Configurable Logic Block (CLB ) having a lookup table (LUT ) with three inputs. The logic blocks are arranged in an 8 * 8 matrix ( array), and could be contacted via switchable connecting lines. In 2009, Freeman was taken for the development of the first FPGAs into the U.S. National Inventors Hall of Fame.

Comparisons

Microprocessors

FPGAs form depending on the configuration, any orders from digital circuit functions, thus providing in principle the ability to process information perfectly parallel. Thus, the resulting data flows in range and depth of information can be optimally adapted to each other. Quick signals to be detected are often fully propagated cyclically so processed in parallel with copies of identical circuits, slowly occurring signals with a single circuit, and space saving.

External processors can execute sequentially with little hardware very complex and nested programs against it. For an FPGA should for each operation a separate piece of hardware to be synthesized, with the limited number of logic gates limiting effect, also the construction of a comparable flexible structure is extremely difficult and time consuming. Therefore, one uses more complex tasks of a so-called soft core CPU which is embedded in the FPGA design. This is similar to the external CPUs and provides a standardized structure that can be programmed in a classical manner in C. Today's FPGAs are sometimes so powerful, so that a variety of 8 -, 16 - to integrate, or 32 -bit CPU cores, but this use of general resources as processor compared to real processors very expensive and energy- consuming. Therefore, there is now FPGAs that several hardware-based CPU cores (ARM -9, PowerPC) included.

Single -core processors, however, are pure finite state machines, living on a fixed hardware and execute their program sequentially, resulting in also significant differences in the design at the implementation of algorithms. However, single-core processors are just dying out, there are now (2010) processors ( Xeon 5680 ), which can execute 24 threads in parallel. Microprocessors often have a fixed prescribed periphery. This is advantage and disadvantage at the same time. On one hand, the peripheral must be not specially created, but can be modified in an FPGA customized approach.

Modern processors SIMD instructions, such as the Intel i7 3930K process up to 96 floating point instructions in parallel (48 multiplications 48 additions ), the achievable flow rate is 3.2 GHz at about 300 GFlops theoretically, of which 250 GFlops are practice -related tasks achievable. Current FPGA can run tens of thousands of fixed-point additions (up to 48 bit) and thousands of fixed-point multiplications (up to 18 × 25 bit) at clock frequencies of 500 MHz at the same time. This means that for processing tasks that can be processed using fixed-point arithmetic, by a factor of 2 to 3 higher processing performance at significantly lower power consumption possible.

Many publications from a wide variety of application areas report on migration of an application software after Configware with acceleration factors from one to four orders of magnitude. Therefore FPGAs find recently received by the Reconfigurable Computing.

ASICs

Advantages of FPGAs

• Significantly lower development costs (as opposed to ASICs are no masks with very high fixed costs required)
• Very short implementation times
• Simply corrected and expanded ( reconfigurable )
• Proved silicon
• Lower design risk since it has to be done not months before the hardware delivery

Disadvantages of FPGAs

• From medium volume higher unit price (as ASICs)
• Lower clock rates ( currently available up to 1.5 GHz, typically 20-500 MHz are realized; offer digital ASICs > 3 GHz)
• Lower logic density (approximately 10 -fold area requirement compared to the same ASIC technology )
• Significantly higher power consumption for the same amount of logic or functions
• Higher sensitivity to particle radiation and electromagnetic waves ( as programmed by RAM cells and not by hard wiring)
• Less flexibility in terms of equipment, for example, embedded memory or analog elements, and also in the IO buffers
• The shorter design cycle and the possibility of very late to be able to still correct errors tempt to perform less functional tests in advance.
• SRAM -based FPGAs ( eg, all these are offered by the market leaders Xilinx and Altera ) must be reloaded at any voltage interruption. This means that the functionality is not available immediately after switching on. The loading can - depending on the technology - take a few seconds. If it is not specific FPGAs with integrated flash memory, additional external components are required for this, such as a vendor-specific EEPROM or flash memory that contains the configuration or a microcontroller with additional flash memory, which performs the charging process.

Manufacturer of FPGAs

• Xilinx - the market leader
• Altera - providers a migration path from the FPGA to structured ASICs
• Lattice - provider of a free 32-bit Open Source soft-core processor as well as GAL- technology
• Atmel - FPGAs, even with additional integrated RAM and AVR microcontroller
• Actel - blocks in FLASH technology, as well as radiation-hardened antifuse FPGAs
• QuickLogic - provider of low-power FPGAs
• Aeroflex - radiation resistant FPGAs
• Silicon Blue - power-saving FPGAs
• Achronix Semiconductor - very fast FPGAs (up to 1.5 GHz) in 22 nm

In addition to the existing vendors have announced two new FPGA company in March 2010, which in various ways a three-dimensional (3D ) each architecture: Tabula and Tier Logic. While Tabula more silicon chips ( dice ) would like one over the other pack in a chip package, Animal Logic will take out the SRAM cells to configure the FPGA from the active silicon area and instead as thin film transistors ( TFT, thin -film transistor ) raise above the active silicon area.